NIMCET Structure Of Instructions In CPU Previous Year Questions (PYQs)
A Place for Latest Exam wise Questions, Videos, Previous Year Papers,
Study Stuff for MCA Examinations
Study Stuff for MCA Examinations
Showing 3 questions
In an instruction execution pipeline, the earliest that the instruction TLB and data TLB
can be accessed are
1
2
3
4
Solution
(1) — Instruction TLB at fetch (to translate the instruction fetch address), Data TLB at memory stage (after effective address is computed in EX).
A CPU uses a $16$-bit instruction format. If $4$ bits are used for the opcode and the remaining bits specify a single memory address, what is the maximum addressable memory space for this instruction format?
1
2
3
4
Solution
Total instruction size is:
$16$ bits
Opcode uses:
$4$ bits
So, remaining bits for memory address are:
$16-4=12$ bits
With $12$ address bits, maximum addressable memory locations are:
$2^{12}=4096$
In a standard machine language instruction, which component identifies the specific operation to be performed, such as addition or data movement?
1
2
3
4
Solution
Opcode stands for Operation Code.
It tells the CPU which operation has to be performed, such as addition, subtraction, data movement, comparison, etc.
Operand tells the data or address on which the operation is performed.
Register is a small storage location inside the CPU.
Immediate address represents data given directly in the instruction.
NIMCET
Online Test Series, Information About Examination,
Syllabus, Notification
and More.
View More
NIMCET
Online Test Series, Information About Examination,
Syllabus, Notification
and More.
View More
Ask Your Question or Put Your Review.
