A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4 -way set associative. The minimum size of the TLB tag is:
🎥 Video solution / Text Solution of this question is given below:
✅ Given Information:
The CPU generates 32-bit virtual addresses with a 4 KB page size. The TLB holds 128 page table entries and is 4-way set associative.
✅ Step 1: Virtual Address Breakdown:
We split the 32-bit virtual address into:
Page Offset: 12 bits (because 4 KB = 212)
Page Number: 20 bits (32 - 12)
✅ Step 2: TLB Breakdown:
The TLB has 128 entries, and with 4-way set associativity, there are:
128 / 4 = 32 sets, so we need 5 bits for the index.
✅ Step 3: Tag Calculation:
The total number of bits for the virtual address is 32: